(1) Field of the Invention
The invention relates to a method of fabricating semiconductor memory devices employing stacked gates, and more particularly, to a method of fabricating memory devices employing stacked gates having an improved interpoly dielectric layer.
(2) Description of the Prior Art
One class of semiconductor memory devices employs floating gates; that is, gates which are completely surrounded by an insulating layer, such as a silicon oxide. The presence or absence of charge in the floating gates represents binary information. These are called electrically programmable read only memories (EPROM). EEPROMS are erasable electrically programmable read only memories. A Flash EEPROM is a device in which the entire array, or a large subset, of the memory cells can be erased simultaneously. A stacked gate Flash EEPROM device has a floating gate which is isolated from the channel and source/drain regions by an insulating layer. An interpoly dielectric layer is formed overlying the floating gate to isolate it from the overlying control gate.
Negative voltage biasing and negative constant current stressing in present Flash memory devices give deleterious results. The major cause of these unfavorable behaviors is the rough surface presented by the floating polysilicon layer of the floating gate. Because of unfavorable surface conditions, a tremendous number of interfacial sites can be generated at the local interface between the bottom oxide layer of the ONO interpoly dielectric stack and the floating polysilicon. These trapping/detrapping sites contribute to the degradation of the integrity of the Flash device. The rough surface of the floating polysilicon can also aggravate the surface condition of the nitride layer of the ONO stack. Therefore, a second imperfect interface results between the silicon nitride layer and the top oxide layer of the ONO stack. The rough surface of the floating polysilicon layer can also result in the formation of convex edges at the top polysilicon layer. These edges can intensify any electrical fields that are present.
U.S. Pat. Nos. 5,625,213 and 5,457,061 to Hong et al show a method of fabricating a Flash EEPROM stacked gate structure wherein the interpoly dielectric layer is formed over the polysilicon layer and both are patterned to form the floating gate. U.S. Pat. No. 5,619,052 to Chang et al teaches forming an ONO interpoly dielectric layer in which the nitride layer is thinner than either of the sandwiching oxide layers.
A principal object of the present invention is to provide an effective and very manufacturable method of fabricating a stacked gate Flash EEPROM device.
Another object of the present invention is to provide an effective and very manufacturable method of fabricating a stacked gate Flash EEPROM device having an improved interpoly dielectric layer.
In accordance with the objects of this invention a new method of fabricating a stacked gate Flash EEPROM device having an improved interpoly dielectric layer is achieved. A gate oxide layer is provided on the surface of a semiconductor substrate. A first polysilicon layer is deposited overlying the semiconductor substrate. The first polysilicon layer is etched away where it is not covered by a mask to form a floating gate. Source and drain regions associated with the floating gate are formed within the semiconductor substrate. An oxide layer is deposited overlying the floating gate and the semiconductor substrate. The oxide layer is polished away until the top of the oxide layer is even with the top of the floating gate. A second polysilicon layer is deposited overlying the oxide layer and the first polysilicon layer of the floating gate wherein the second polysilicon layer has a smooth surface. An interpoly dielectric layer is deposited overlying the second polysilicon layer. A third polysilicon layer is deposited overlying the interpoly dielectric layer. The third polysilicon layer and the interpoly dielectric layer are etched away where they are not covered by a mask to form a control gate overlying the floating gate. An insulating layer is deposited overlying the oxide layer and the control gate. Contact openings are formed through the insulating layer to the underlying control gate and to the underlying source and drain regions. The contact openings are filled with a conducting layer to complete the fabrication of the Flash EEPROM device.
Also in accordance with the objects of this invention, a stacked gate Flash EEPROM device having an improved interpoly oxide layer is described. A polysilicon floating gate having an oxide layer thereunder lies on the surface of a semiconductor substrate. Associated source and drain regions lie within the semiconductor substrate. A polysilicon layer overlies the floating gate wherein the top surface of the polysilicon layer is smooth. An interpoly dielectric layer overlies the polysilicon layer. A control gate overlies the interpoly dielectric layer. An insulating layer overlies the semiconductor substrate and the control gate. A patterned metal layer overlies the insulating layer and extends through contact openings in the insulating layer to the underlying control gate and to the underlying source and drain regions to complete the Flash EEPROM device.